Extended Life Processors and Peripherals - The company has established a World-Class Reputation for solving obsolescence problems by developing pin compatible integrated circuits to replace those that have been discontinued by the original manufacturer. Replacement ICs are form, fit, and function, below are some examples; other ICs are also available. Intel® examples include: 80C186/188EB, 80L188EB, 80C186/188XL, 82527 Serial Communications Controller (CAN Controller) AMD® examples include: 186/188ES and 186/188EM
Industrial Networking Solutions - Real-Time Industrial Ethernet semiconductor solutions for Profinet and EtherNet/IP. Based on the Innovasic fido1100 communications controller chip, these complete embedded networking solutions include all software, stacks, and a production ready "drop-in" reference design to accelerate your product development and provide the lowest recurring production cost. Plug-in modules are available for the fastest time to market. The embedded designs allow a very easy transition to the lowest bill of materials cost.
Circuit Simulation: FineSim Spice and FineSim Pro defines a new paradigm in full-chip circuit-level simulation, enabling the simulation of the most challenging analog/mixed-signal SoCs with SPICE accuracy and unprecedented performance.
Analysis: QCP is a next-generation standalone extraction tool that provides the performance boost and accuracy required for designs at 40 nm and below. Built on a new architecture, QCP provides significant performance gains that eliminate the extraction bottleneck in timing closure. Its elegant multi-corner extraction solution scales well with the explosion in the number of PVT corners required for sign-off. With QuickCap® integrated under the hood, designers can dial-in the capacitance accuracy required for analyzing critical nets.
Synthesis: Talus RTL is a comprehensive RTL synthesis solution that can be used standalone or integrated within Magma’s Talus IC implementation system. It is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process without sacrificing design quality or the delivery schedule.
